1. Field of the Invention
The invention relates in general to a bumping process and a structure thereof, and more particularly to a bumping process and a structure thereof achieved by electroplating process.
2. Description of the Related Art
Along with the rapid advance in science and technology in the semiconductor industry, electronic products incorporating semiconductor components have become indispensable to modern people in their everydayness. In response to the design trend of slimness, light weight and compactness, high density semiconductor packaging technology such as flip-chip package is developed. The flip chip in package manufacturing process possesses the features of excellent electric characteristics, high input/output contact density, reducing the size of IC chip and increasing wafer output, is considered to have great potential. The bump process is crucial to the flip chip in packaging technology.
Referring to FIGS. 1A˜1H, a flowchart of a conventional bumping process is shown. Firstly, refer to FIG. 1A, a wafer 10 whose surface has a pad 11 disposed thereon is provided, and there is a passivation layer 20 covering the surface of the pad 11 and the surface of the wafer but exposing a portion of the pad 11. Next, refer to FIG. 1B, a metallurgy layer 30b is deposited. Then, refer to FIG. 1C, a photo-resist layer 40 is coated on the -metallurgy layer 30b. Next, refer to FIG. 1D, the photo-resist layer 40 is patterned and an opening 60 is formed above the pad 11. Then, refer to FIG. 1E, a solder layer 50 is formed in the opening 60 by electroplating process. Next, refer to FIG. 1F, the photo-resist layer 40 is removed to expose the solder layer 50. Then, refer to FIG. 1G, the portion of the metallurgy layer 30b exposed outside the solder layer 50 is etched to form an under-bump metallurgy (UBM) layer 30. During the etching process, the solder layer 50 will be damaged and oxidized, so the oxides formed on the surface of the solder layer 50 need to be detached. Lastly, refer to FIG. 1H, a conductive bump 51 is formed by reflowing process.
As disclosed above, in FIG. 1G, the etching process removes the metallurgy layer 30b, but the same time etches the surface of the solder layer 50, causing oxides to be formed in the surface of the solder layer 50, making the electric resistance too high. Therefore, a manufacturing process of detaching the oxides has to be added, wasting both the labor and the costs. Furthermore, since the etching direction in the etching process is not consistent, lateral etching 30a will occur to the peripheral of the UBM layer 30 under the solder layer 50, making the solder layer 50 unstable and will break or come off easily. The lateral etching 30a occurs under the solder layer 50 and is hard to be detected, making the quality of the conductive bump 51 unstable.